NXP Semiconductors /LPC11Axx /DAC /CR

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Interpret as CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0VALUE0 (FAST)BIAS 0 (IMMEDIATE)TRIG0RESERVED 0 (FALLING)EDGESEL 0 (TRIGERD)TRIGERD 0RESERVED

TRIG=IMMEDIATE, BIAS=FAST, EDGESEL=FALLING

Description

D/A control register

Fields

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

VALUE

After the selected settling time after a conversion begins, the voltage on the AOUT pin (with respect to VSS) is VALUE x (V DD/1024).

BIAS

Settling time

0 (FAST): The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.

1 (SLOW): The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.

TRIG

The value written to this field determines whether conversion begins immediately after this register is written, or whether conversion is delayed until a selected event occurs.

0 (IMMEDIATE): Conversion begins when this register is written, and AOUT begins to change to the new voltage immediately. For all other values in this field, AOUT remains at its previous voltage until the selected event has occurred.

1 (COMPLEVELOUT): Conversion is triggered by the selected edge(s) on the analog comparator (level) output

2 (ATRG0EDGE): Conversion is triggered by the selected edge(s) on ATRG0.

3 (ATRG1EDGE): Conversion is triggered by the selected edge(s) on ATRG1.

4 (CT32B1_MAT0EDGE): Conversion is triggered by the selected edge(s) on CT32B1_MAT0 [2].

5 (CT32B1_MAT1EDGE): Conversion is triggered by the selected edge(s) on CT32B1_MAT1[2].

6 (CT16B1_MAT0EDGE): Conversion is triggered by the selected edge(s) on CT16B1_MAT0[2].

7 (CT16B1_MAT1EDGE): Conversion is triggered by the selected edge(s) on CT16B1_MAT1[2].

RESERVED

Reserved.

EDGESEL

For non-zero values of TRIG, this field selects when the conversion is triggered:

0 (FALLING): Falling edges

1 (RISINGs): Rising edges

2 (DUALEDGE): Both edges

3 (DUALEDGE): Both edges

TRIGERD

If the TRIG field (above) is non-zero, this bit is set when a conversion is triggered, and is cleared by any write to this register.

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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